Hello! My name is Dylan Weber. I'm a forward thinking Purdue University computer engineering graduate specializing in computer architecture and embedded devices. I'm able to think creatively to deliver solutions through continuous improvement. I possesses great attention to detail and high-quality work and can manage concurrent projects in a fast-paced, deadline driven environment.
Renesas RL, Atmel ATmega/ATtiny, STMicroelectronics STM32, Espressif ESP8266, Espressif ESPS32
KiCad, Mentor Graphics ModelSim, Linux, GTK, PKCS#11, CMake, OpenGL, Vulkan
An ESP32-based embedded microcontroller device designed to input a doorbell signal and send the information to an MQTT server on the internet or local network. It uses a captive portal Wi-Fi login mechanism and automatic discovery to the MQTT server on the network. Source code for the project can be found on Github.
This board runs off a variable input DC range of 4.7V to 30V, with reverse-input protection and in-rush current protection. The internal buck-regulator supplies the ESP32 with 3.3V. The board also has automatic programming circuitry so an attached USB to UART converter can automatically put the board into programming mode and reset once done.
This is the transmitter board, which sends the doorbell signal. A seperate device, which recieves the signal and activates a relay, can be found here.
An STM32-based accelerometer and gyroscope reader using the MPU-6050 accelerometer and gyroscope unit which uses an 16x2 OLED display to show the user the current acceleration or angular velocity of the device. The user interface buttons allow the user to freeze the reading, change measurement ranges, and switch modes. It runs off a single 9V battery.
An STM32-based device that uses a LIDAR sensor, accelerometer, and gryoscope to act like a mix between a radar speed gun and a measuring tape. Simply point to location A, press the trigger, and then point to location B and it will measure the distance between the two points. Includes a large graphical screen & microSD card functionality.
A dual core MIPS processor design with seperate data and instruction caches. Uses a 5-stage pipeline design to increase clock frequency in addition to multiple optimizations such as branch prediction and branch target buffers.